Here is a state table (abbreviated) for a 4-bit counter register:
ld i3 i2 i1 i0 o3 o2 o1 o0 | o3' o2' o1' o0' -------------------------------------------- 0 - - - - 0 0 0 0 | 0 0 0 1 0 - - - - 0 0 0 1 | 0 0 1 0 0 - - - - 0 0 1 0 | 0 0 1 1 0 - - - - 0 0 1 1 | 0 1 0 0 0 - - - - 0 1 0 0 | 0 1 0 1 0 - - - - 0 1 0 1 | 0 1 1 0 0 - - - - 0 1 1 0 | 0 1 1 1 0 - - - - 0 1 1 1 | 1 0 0 0 0 - - - - 1 0 0 0 | 1 0 0 1 0 - - - - 1 0 0 1 | 1 0 1 0 0 - - - - 1 0 1 0 | 1 0 1 1 0 - - - - 1 0 1 1 | 1 1 0 0 0 - - - - 1 1 0 0 | 1 1 0 1 0 - - - - 1 1 0 1 | 1 1 1 0 0 - - - - 1 1 1 0 | 1 1 1 1 0 - - - - 1 1 1 1 | 0 0 0 0 1 c3 c2 c1 c0 - - - - | c3 c2 c1 c0As you can see, the counter register behaves like an ordinary counter when the ld signal is 0 and as a register when the ld signal is 1.